Plasma display panel and method of manufacturing the same

ABSTRACT

Disclosed here is a plasma display panel having stable addressing characteristics and a method of manufacturing a plasma display panel having such a reliable structure. According to the plasma display panel and the manufacturing method, on back plate ( 2 ) that confronts front plate ( 1 ) having scan electrodes ( 6 ) and sustain electrodes ( 7 ) thereon, data electrodes ( 10 ), first dielectric layer ( 17 ) disposed to cover the data electrodes, priming electrodes ( 15 ), and second dielectric layer ( 18 ) disposed to cover the priming electrodes are formed in the order named; at the same time, the softening temperatures of the materials forming the components disposed on the back plate are determined so as to become lower in the order named. The temperature setting protects first dielectric layer ( 17 ) from deterioration or deformation, improving dielectric voltage between data electrodes ( 10 ) and priming electrodes ( 15 ).

TECHNICAL FIELD

The present invention relates to a plasma display panel used for awall-mount TV and a large sized monitor, and also relates to a method ofmanufacturing the same.

BACKGROUND ART

In a plasma display panel (hereinafter referred to as a PDP) with analternate current (AC) discharging type, AC surface discharge PDPs havebeen dominating. Such a PDP has a front plate and a back plate that aremade of a glass substrate. Scan electrodes and sustain electrodes, whichare responsible for surface discharge, are disposed on the front plate,and data electrodes are disposed on the back plate. The two plates areoppositely disposed so that the electrodes disposed on each plate formsa grid pattern, and sealed at the peripheries with a sealing material,such as glass frit. A sealed clearance formed between the two plates isa discharge space divided into discharge cells by barrier ribs. Eachcell has a phosphor layer.

In a PDP structured above, gas discharge generates ultraviolet light, bywhich phosphors responsible for red (R), green (G), and blue (B) areexcited to generate visible light of respective colors.

In driving operation of the PDP, one field is divided into a pluralityof sub-fields. Combining the sub-fields to be lit provides the PDP withgradation display. Each sub-field has a reset period, an address period,and a sustain period. To display images on the screen, voltage having adifferent waveform according to each period is applied to theelectrodes. In the reset period, for example, positive pulse voltage isapplied to all the scan electrodes to form necessary wall charges on aprotective film provided over a dielectric layer covering the scanelectrodes and sustain electrodes, and on the phosphor layers. In theaddress period, the scan electrodes undergo scanning in which negativescanning pulses are sequentially applied to all the scan electrodes. Todisplay images on the screen, positive data pulses are applied to thedata electrodes during the scanning. This causes discharge between thescan electrodes and the data electrodes, thereby forming wall charges onthe surface of the protective film on the scan electrodes.

In the sustain period following the address period, a voltage adequatefor sustaining discharge for a predetermined period is applied betweenthe scan electrodes and the sustain electrodes. The application ofvoltage generates discharge plasma between the scan electrodes and thesustain electrodes, by which an excited phosphor layer emits light for aperiod. On the other hand, in the discharge space to which no data pulseis applied during the address period, no discharge occurs andaccordingly, neither excitation nor light emitting of the phosphorlayers.

In the PDP above, a perceptible discharge delay generated in the addressperiod invites an unstable addressing operation. Increasing the addresstime so that the addressing operation is satisfactorily carried outinevitably shortens the time for the sustain period, which results in apoor luminescence.

To address the problems above, there has been a suggestion in which aPDP and a driving method capable of minimizing the discharge delay.According to the suggestion, an auxiliary discharge electrode isdisposed on the front plate to generate surface auxiliary dischargespreading in a plane near by the front plate. As a result, primingdischarge occurs, contributing to minimized discharge delay.

The PDP introduced in the suggestion above, however, has severalproblems: insufficient reduction of the discharge delay in the addressperiod; insufficient operation margin of the auxiliary discharge;unstable operations influenced by undesired false discharge. Inaddition, the auxiliary discharge occurs in the surface of the frontplate, and therefore an amount of priming particles larger thannecessary for priming is fed to an adjacent discharge cell, which hasoften caused crosstalk.

DISCLOSURE OF THE INVENTION

The PDP of the present invention contains a first electrode and a secondelectrode disposed on a first substrate so as to be parallel with eachother; a third electrode disposed on a second substrate confronting thefirst substrate via a discharge space so as to be orthogonal to thefirst electrode and the second electrode; a fourth electrode disposed onthe second substrate so as to be parallel with the first and secondelectrodes and to be positioned closer to the first and secondelectrodes than the third electrode; and a barrier rib disposed on thesecond substrate so as to separate a plurality of main discharge cells,which are formed of the first, second, and third electrodes, from aplurality of priming discharge cells, which are formed of the firstelectrode and the fourth electrode or formed of the second electrode andthe fourth electrode. In the aforementioned PDP, at least the thirdelectrodes are covered with a first dielectric layer and the fourthelectrodes are disposed on the first dielectric layer. In addition, thefourth electrodes are made of material having a softening temperaturelower than that of material forming the first dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a section view illustrating a PDP of a first exemplaryembodiment of the present invention.

FIG. 2 is a plan view schematically showing the electrode layout on theside of the front plate of the PDP.

FIG. 3 is a perspective view that schematically shows the side of theback plate of the PDP.

FIG. 4 shows an example of driving waveforms for driving the PDP.

FIG. 5 is a flowchart showing the process of manufacturing the backplate of the PDP.

FIG. 6 is a section view illustrating deformation observed in aconventional priming electrode.

FIG. 7 is a section view illustrating bubbles generated in aconventional first dielectric layer.

FIG. 8 is a flowchart showing a process of simultaneous baking of theback plate of the PDP of a second exemplary embodiment.

FIG. 9 is a flowchart showing another process of simultaneous baking ofthe back plate of the PDP.

DETAILED DESCRIPTION OF CARRYING OUT OF THE INVENTION

The exemplary embodiments of the present invention are describedhereinafter with reference to the accompanying drawings.

First Exemplary Embodiment

Here will be described a PDP and a manufacturing method of the firstexemplary embodiment with reference to FIGS. 1 through 5. It is to beunderstood that the present invention is not limited to the formsdescribed here.

FIG. 1 is a section view illustrating the PDP of the first exemplaryembodiment of the present invention. FIG. 2 is a plan view schematicallyshowing the electrode layout on the side of the front plate of the PDP.FIG. 3 is a perspective view that schematically shows the side of theback plate of the PDP.

As shown in FIG. 1, glass-made front plate 1 as the first substrate andglass-made back plate 2 as the second substrate are oppositely disposedvia discharge space 3 therebetween. Discharge space 3 is filled with agas, such as neon (Ne), xenon (Xe), that radiates ultraviolet lightthrough discharging. On front plate 1, electrode array, which is formedof pairs of scan electrodes 6 (i.e., the first electrode) and sustainelectrodes 7 (i.e., the second electrode) is disposed in a stripearrangement. Each scan electrode 6 is formed of transparent electrode 6a and metallic bus line 6 b; similarly, each sustain electrode 7 isformed of transparent electrode 7 a and metallic bus line 7 b. Bus lines6 b and 7 b are made of material providing higher conductivity, such assilver (Ag), and are laid on transparent electrodes 6 a and 7 a,respectively. Scan electrodes 6 and sustain electrodes 7 are coveredwith front-plate dielectric layer 4 and over which, protective film 5 isformed. Scan electrodes 6 and sustain electrodes 7 are, as shown in FIG.1 and FIG. 2, alternately arranged by two rows of each electrode.Between adjacent scan electrodes 6 and between adjacent sustainelectrodes 7, light absorption layer 8 is disposed to intensify contrastwhen light is emitted. Auxiliary electrode 9 is disposed on lightabsorption layer 8 between adjacent scan electrodes 6 so as to connectto one of adjacent scan electrodes 6 at an end (i.e., non-display area)of the PDP.

On back plate 2, as shown in FIG. 1 and FIG. 3, a plurality ofstrip-shaped data electrodes 10 (as the third electrode) is disposed inparallel with each other so as to be orthogonal to scan electrodes 6 andsustain electrodes 7. First dielectric layer 17 is formed to cover dataelectrodes 10. Priming electrodes 15 (as the fourth electrode) areformed on first dielectric layer 17 at a section corresponding to whereauxiliary electrode 9 is disposed on front plate 1 so as to be parallelto auxiliary electrode 9. Second dielectric layer 18 is laid over firstdielectric layer 17 to cover priming electrodes 15. Barrier rib 11 isdisposed on second dielectric layer 18. Barrier rib 11 is a divider ofthe discharge cells that are formed of scan electrodes 6, sustainelectrodes 7, and data electrodes 10. Barrier rib 11 has vertical wall11 a and horizontal wall 11 b. Vertical wall 11 a is orthogonal to scanelectrodes 6 and sustain electrodes 7 on front plate 1, or parallel todata electrodes 10. Horizontal wall 11 b is disposed so as to crossvertical wall 11 a. Vertical wall 11 a and horizontal wall 11 b form gap13 between main discharge cells 12 and priming discharge cells 16 havingpriming electrode 15. That is, gap 13 and priming discharge cell 16 arealternately arranged via main discharge cell 12. Phosphor layer 12 isformed in main discharge cell 12.

As shown in FIG. 3, data electrodes 10 are covered with first dielectriclayer 17 and on which, priming electrodes 15 are disposed. Further,priming electrodes 15 are covered with second dielectric layer 18. Thatis, compared to the distance between data electrode 10 and protectivefilm 5 in main discharge cell 12, the distance between priming electrode15 and protective film 5 in priming discharge cell 16 becomes shorter bythe thickness of first dielectric layer 17.

Next will be described how an image data is shown on a PDP. According tothe PDP in the embodiment, one field is divided into a plurality ofsub-fields each of which has a weight of luminance in binaryrepresentation. Combining the sub-field to be lit provides the PDP withgradation display. Each sub-field has a reset period, an address period,and a sustain period.

FIG. 4 shows an example of driving waveforms for driving the PDP of theembodiment of the present invention. In the reset period, positive pulsevoltage is applied to all scan electrode Y (corresponding to scanelectrode 6 in FIG. 1) in the priming discharge cell (corresponding topriming discharge cell 16 in FIG. 1) in which priming electrode Pr(corresponding to priming electrode 15 in FIG. 1) is formed, whereby areset operation is performed between the auxiliary electrode(corresponding to auxiliary electrode 9 in FIG. 1) and priming electrodePr. During the address period that follows the reset period, positivevoltage is applied to priming electrode Pr. In the successive sustainperiod, alternating voltage enough for maintaining discharge is appliedbetween the scan electrode and the sustain electrode. The application ofvoltage generates discharge plasma between scan electrode Y and sustainelectrode X (corresponding to sustain electrode 7 in FIG. 1) for apredetermined period, which excites the phosphor layers forlight-emitting. On the other hand, the discharge cells that have noapplication of voltage in the address period have no discharge;accordingly, the phosphor layers in the cells have no excitation andtherefore no light emitting.

In the priming discharge cell, when scan pulse SPn is applied to scanelectrode Yn, priming discharge occurs between priming electrode Pr andthe auxiliary electrode, providing the main discharge cell(corresponding to main discharge cell 12 in FIG. 1) with primingparticles. Next, scan pulse SP_(n+1) is applied to scan electrodeY_(n+1) of the n+1^(th) main discharge cell. At this time, the primingparticles have already been fed by the priming discharge that occurredjust before the application of voltage. This can minimize the delay indischarge in the next address period. Although the description herefocuses on a driving sequence of a one field, operations in othersub-fields similarly work. Applying positive voltage to primingelectrode Pr in the address period, as shown in the driving waveforms inFIG. 4, encourages a reliable discharge operation described above. It ispreferable that the voltage applied to priming electrode Pr in theaddress period should be greater than that applied to data electrode D(corresponding to data electrode 10 in FIG. 1).

In the structure in which priming electrode 15 is formed on firstdielectric layer 17 in priming discharge cell 16, first dielectric layer17 can provide dielectric voltage between data electrode 10 and primingelectrode 15—as long as first dielectric layer 17 is properly formed,contributing to stable priming discharge and address discharge. Besides,in priming discharge cell 16 where priming electrode 15 is formed onfirst dielectric layer 17, the distance between priming electrode 15 andauxiliary electrode 9 becomes shorter than that between data electrode10 and scan electrode 6 in main discharge cell 12. The structure aboveallows main discharge cell 12, which corresponds to scan electrode 6connected to auxiliary electrode 9, to have priming discharge withreliability and stability prior to the address discharge. Thiscontributes to minimized delay in discharge in main discharge cell 12.

FIG. 5 is a flowchart showing the process of manufacturing the backplate of the PDP of the embodiment.

In step 1, as shown in FIG. 5, prepare the back glass-substrate as backplate 2, and then form data electrodes 10 on the back glass-substrate insteps 2 and 3. More specifically, in step 2, apply silver (Ag) paste tothe back glass-substrate and then form silver (Ag) line having a widthof 150 μM by photolithography. Of the glass components forming dataelectrodes 10, at least one component has a softening temperature of590° C. In step 3, harden the silver (Ag) line by baking at 600° C. tocomplete data electrode 10. Next, first dielectric layer 17 is formed insteps 4 and 5. As the materials of first dielectric layer 17,ZnO—B₂O₃—SiO₂-based mixture, PbO—B₂O₃—SiO₂-based mixture,PbO—B₂O₃—SiO₂—Al₂O₃-based mixture, PbO—ZnO—B₂O₃—SiO₂-based mixture,Bi₂O₃—B₂O₃—SiO₂-based mixture, or the like, can be employed. Firstdielectric layer 17 of the first embodiment of the present invention isa mixture of 65-70 wt % PbO; 5 wt % B₂O₃; and 25-30 wt % SiO₂, having asoftening temperature of 580° C. The softening temperature can beflexibly determined by increasing or decreasing the PbO content. In step4, mix the materials of first dielectric layer 17 into a paste and applyit over data electrode 10. The applying method is not limited to aspecific one; the paste can be applied in a well know manner, such asroll coating, slit die coating, doctor blade method, screen printing, oroff-set printing. In the first embodiment of the present invention, theapplying thickness of the paste of first dielectric layer 17 shouldpreferably range from 5 to 40 μm. Applying the paste with a thickness of5 μm or more can lessen the unevenness of the surface of firstdielectric layer 17—due to data electrodes 10 disposed thereunder—afterthe baking process. The applying thickness of first dielectric layer 17depends on the mineral element content in the paste. In step 5, thepaste is baked at 585° C. to complete first dielectric layer 17. Thebaking temperature of first dielectric layer 17 is lower than thesoftening temperature of data electrode 10, so that deterioration ordeformation in data electrode 10 can be suppressed during the bakingprocess of first dielectric layer 17.

In the next steps 6 and 7, priming electrode 15 is formed. In step 6,silver (Ag) paste is applied to first dielectric layer 17 in a manneralmost the same as that for forming data electrode 10 in step 2. Ofglass components forming priming electrode 15, at least one componenthas a softening temperature of 570° C. In step 7, the paste is baked at575° C. to complete priming electrode 15. The baking temperature at thistime (i.e., 575° C.) is lower than 580° C. that is the softeningtemperature of first dielectric layer 17, and is not less than 570° C.that is the softening temperature of the materials forming primingelectrode 15. That is, deterioration or deformation in first dielectriclayer 17 can be suppressed during the baking process of primingelectrode 15.

Conventionally, the softening temperature of priming electrode 15 hasnot always determined to be lower than that of first dielectric layer17. Therefore, the baking temperature of priming electrode 15 has oftenexceeded the softening temperature of first dielectric layer 17. In thiscase, when priming electrode 15 undergoes the baking process, underlyingfirst dielectric layer 17 softens, and thermally deformed primingelectrode 15 sinks into softened first dielectric layer 17. As a result,priming electrode 15 and data electrode 10 cannot have a properinsulation distance therebetween. FIG. 7 is a section view illustratingbubbles generated in a conventional first dielectric layer. As primingelectrode 15 is baked and thermally deformed, first dielectric layer 17also softens. This has often generated bubbles in first dielectric layer17 under priming electrode 15. However, the manufacturing process of thefirst exemplary embodiment of the present invention can protect firstdielectric layer 17 from deterioration or deformation during the bakingprocess of priming electrode 15, eliminating a cause of dielectricbreakdown. As a result, a PDP with high reliability in operation can beprovided.

Steps 8 and 9 are for forming second dielectric layer 18. Seconddielectric layer 18 is formed in the same manner as first dielectriclayer 17 formed in steps 4 and 5. The composition of second dielectriclayer 18 differs from that second dielectric layer 18 differs from thatof first dielectric layer 17 in having approx. 5 wt %-increased PbOcontent. The softening temperature of second dielectric layer 18 isdetermined at 560° C., which is a 20° C.-lowered setting than thesoftening temperature of first dielectric layer 17. In step 8, the pasteprepared for second dielectric layer 18 is applied on first dielectriclayer 17 so as to cover priming electrode 15 by screen printing, orother methods described earlier. In step 9, the paste is baked at 565°C. to complete second dielectric layer 18. The baking temperature atthis time (565° C.) is determined so as to be lower than the softeningtemperatures of the materials forming priming electrode 15 (570° C.);first dielectric layer 17 (580° C.); and data electrode 10 (590° C.),and so as to be higher than the softening temperature of the materialforming second dielectric layer 18. Therefore the temperature settingcan protect priming electrode 15, first dielectric layer 17, and dataelectrode 10 from deterioration or deformation during the baking processof second dielectric layer 18, eliminating a cause of dielectricbreakdown on priming electrode 15.

Steps 10 and 11 are for forming barrier rib 11 and phosphor layers 14.In step 10, photosensitive paste including a glass component and aphotosensitive organic component is applied on second dielectric layer18 and then dried. Through a photo process, patterns of vertical wall 11a and horizontal wall 11 b, which form the space between main dischargecells 12, the space between priming discharge cells 16, and gap 13, areformed. Besides, phosphor layers 14 for red (R), green (G), and blue (B)are formed by filling in main discharge cells 12. The softeningtemperatures of barrier rib 11 and phosphor layers 14 are 550° C. orlower. In step 11, barrier rib 11 and phosphor layers 14 aresimultaneously baked at 555° C. to complete them. The baking temperatureat that time is set to be lower than each softening temperature ofunderlying second dielectric layer 18, priming electrode 15, firstdielectric layer 17, and data electrode 10. The temperature setting canprotect the underlying components from deterioration or deformationduring the baking process. As a further advantage, the underlyingcomponents make a foundation to support top-situated barrier rib 11.Minimizing the deformation in the underlying components can providebarrier rib 11 with consistent dimensional accuracy. As a result, a PDPwith a high accuracy of dimension can be obtained.

Back substrate 2 is thus completed through the process above.

Second Exemplary Embodiment

Next will be described the second exemplary embodiment of the presentinvention with reference to FIG. 8.

In the first exemplary embodiment, data electrodes 10, first dielectriclayer 17, priming electrodes 15, second dielectric layer 18, and barrierrib 11 are separately baked with the softening temperature of themdetermined in higher-to-lower order named, whereby all the componentsforming the back substrate are considerably protected againstdeterioration and deformation. Among the components above, deformationof first dielectric layer 17 seriously affects the dielectric breakdown.The following method, which focuses on protecting only first dielectriclayer 17 from deformation, can simplify the manufacturing process. Thatis, the softening temperatures of first dielectric layer 17, primingelectrode 15, second dielectric layer 18 are determined inhigher-to-lower order named; the softening temperature of data electrode10 is determined to be the same as that of first dielectric layer 17 andthe two are baked at the same time; and each softening temperature ofbarrier rib 11 and phosphor layer 14 is determined to be the same asthat of second dielectric layer 18 and the three are baked at the sametime.

The second exemplary embodiment describes a manufacturing process inwhich data electrode 10 and first dielectric layer 17 undergo thesimultaneous baking, while second dielectric layer 18, barrier rib 11,and phosphor layer 14 undergo the simultaneous baking.

FIG. 8 is a flowchart showing a process of simultaneous baking of theback plate of the PDP of a second exemplary embodiment.

In step 1, as shown in FIG. 8, prepare the back glass-substrate as backplate 2. In step 2, apply silver (Ag) paste to the back glass-substrateand then form silver (Ag) line having a width of 150 μm byphotolithography. The precursor for data electrode 10 is thus formed. Ofthe glass components forming data electrodes 10, at least one componenthas a softening temperature of 580° C.

Step 3 is for forming the precursor layer for first dielectric layer 17.As the materials of first dielectric layer 17, ZnO—B₂O₃—SiO₂-basedmixture, PbO—B₂O₃—SiO₂-based mixture, PbO—B₂O₃—SiO₂—Al₂O₃-based mixture,PbO—ZnO—B₂O₃—SiO₂-based mixture, Bi₂O₃—B₂O₃—SiO₂-based mixture, or thelike, can be employed. First dielectric layer 17 of the embodiment ofthe present invention is a mixture of 65-70 wt % PbO; 5 wt % B₂O₃; and25-30 wt % SiO₂, having the same softening temperature as data electrode10. The softening temperature can be flexibly determined by increasingor decreasing the PbO content. Mix the materials of first dielectriclayer 17 into a paste and apply it over the precursor for data electrode10. The applying method is not limited to a specific one; the paste canbe applied or printed in a well know manner, such as roll coating, slitdie coating, doctor blade method, screen printing, and off-set printing.In the second embodiment of the present invention, the applyingthickness of the paste of first dielectric layer 17 should preferablyrange from 5 to 40 μm. Applying the paste with a thickness of 5 μm ormore can lessen the unevenness of the surface of first dielectric layer17—due to data electrodes 10 disposed thereunder—after the bakingprocess. The applying thickness of first dielectric layer 17 depends onthe mineral element content in the paste.

In step 4, the precursor for data electrode 10 and the precursor layerfor first dielectric layer 17 are simultaneously baked at 585° C. Dataelectrode 10 and first dielectric layer 17 are thus completed.

In the next steps 5 and 6, priming electrode 15 is formed. In step 5,silver (Ag) paste is applied to first dielectric layer 17 in a manneralmost the same as that for forming the precursor for data electrode 10in step 2. Of glass components forming priming electrode 15, at leastone component has a softening temperature of 570° C. In step 6, thepaste is baked at 575° C. to complete priming electrode 15. The bakingtemperature at this time (i.e., 575° C.) is lower than the softeningtemperatures of the materials forming first dielectric layer 17 (580°C.) and data electrode 10 (580° C.); and is not less than the softeningtemperature of the materials forming priming electrode 15 (570° C.). Thetemperature setting can protect first dielectric layer 17 fromdeterioration or deformation during the baking process of primingelectrode 15, eliminating a cause of dielectric breakdown on primingelectrode 15. As a result, a PDP with high reliability in operation canbe provided.

Step 7 is for forming the precursor layer for second dielectric layer18. Second dielectric layer 18 is formed in the same manner as firstdielectric layer 17 formed in steps 3. To form the precursor layer forsecond dielectric layer 18, paste is applied on first dielectric layer17 so as to cover priming electrode 15 by screen printing, or othermethods described earlier. The composition of second dielectric layer 18differs from that of first dielectric layer 17 in having approx. 5 wt%-increased PbO content. The softening temperature of second dielectriclayer 18 is determined at 560° C. or lower, which is a 20° C.-loweredsetting than the softening temperature of first dielectric layer 17.

Step 8 is for forming barrier rib 11 and the precursor layer forphosphor layer 14. First, photosensitive paste including a glasscomponent and a photosensitive organic component is applied on seconddielectric layer 18 and then dried. Through a photo process, patterns ofvertical wall 11 a and horizontal wall 11 b, which form the spacebetween main discharge cells 12, the space between priming dischargecells 16, and gap 13, are formed. Besides, phosphor layers 14 for red(R), green (G), and blue (B) are formed by filling in main dischargecells 12. The softening temperatures of barrier rib 11 and phosphorlayers 14 are determined to be the same as that of second dielectriclayer 18.

In step 9, the precursor layer for second dielectric layer 18, barrierrib 11, and the precursor layer for phosphor layer 14 are simultaneouslybaked at 565° C. to complete them. Second dielectric layer 18, barrierrib 11, and phosphor layer 14 are thus completed. The baking temperatureat that time (565° C.) is lower not only than the softening temperatureof the materials forming priming electrode 15 (570° C.) but also thanthe lower softening temperature of the materials forming firstdielectric layer 17 and data electrode 10, and is not less than thehighest softening temperature of the materials for second dielectriclayer 18, barrier rib 11, and phosphor layer 14. The temperature settingcan protect priming electrode 15, first dielectric layer 17, and dataelectrode 10 from deterioration or deformation during the bakingprocess. As a further advantage, the aforementioned components make afoundation to support top-situated barrier rib 11. Minimizing thedeformation in the components can provide barrier rib 11 with consistentdimensional accuracy. As a result, a PDP with a high accuracy ofdimension can be obtained.

As described above, data electrode 10 and first dielectric layer 17 aresimultaneously baked; on the other hand, second dielectric layer 18,barrier rib 11, and phosphor layer 14 are simultaneously baked.Introducing the simultaneous baking can simplify the manufacturing stepsof back plate 2.

Moreover, priming electrode 15, second dielectric layer 18, barrier rib11, and phosphor layer 14 can be simultaneously baked. This can furthersimplify the manufacturing process.

FIG. 9 is a flowchart showing another process of simultaneous baking ofthe back plate of the PDP of the embodiment of the present invention.The processes of step 1 through step 4 of FIG. 9 are the exactly aliketo those of the process in FIG. 8.

Step 5 is for forming the precursor for priming electrode 15. Of glasscomponents forming priming electrode 15, at least one component has asoftening temperature of 560° C.

Step 6 is for forming the precursor layer for second dielectric layer18. Here in the description, the softening temperature of seconddielectric layer 18 is determined to be the same as that of primingelectrode 15.

Step 7 is for forming barrier rib 11 and the precursor layer forphosphor layer 14. The softening temperature of barrier rib 11 andphosphor layer 14 are also determined to be the same as that of primingelectrode 15.

Step 8 is for forming priming electrode 15, second dielectric layer 18,barrier rib 11, and phosphor layer 14. In this step, the precursor forpriming electrode 15, the precursor layer for second dielectric layer18, barrier rib 11, and the precursor layer for phosphor layer 14 aresimultaneously baked at 565° C.

The baking temperature at that time (565° C.) is lower than the lowersoftening temperature (580° C.) of the materials forming data electrode10 and first dielectric layer 17, and is not less than the highestsoftening temperature (560° C.) of the materials for priming electrode15, second dielectric layer 18, barrier rib 11, and phosphor layer 14.The temperature setting can protect first dielectric layer 17 fromdeterioration or deformation during the baking process.

Baking priming electrode 15 together with second dielectric layer 18 andthe components above can further simplify the manufacturing process.These components are baked at a temperature lower than the softeningtemperature of first dielectric layer 17. This protects first dielectriclayer 17 from deterioration or deformation during the baking process,eliminating a cause of dielectric breakdown on priming electrode 15. Asa result, a PDP with high reliability in operation can be provided.

Although lead (Pb)-based mixture is used for the material of firstdielectric layer 17 and second dielectric layer 18 in the description,zinc (Zn)-, or bismuth (Bi)-based mixture can be employed for them. Inthis case, the softening temperature of the material can be flexiblydetermined by increasing or decreasing the Zn or Bi content.

The wording of the “same” softening temperature used through thedescription means substantially the same temperature. Therefore, adifference between the materials that are baked at the same time isnegligible in the scope that the purpose of the present invention can berealized as is intended.

INDUSTRIAL APPLICABILITY

The PDP of the present invention contains, as described above, primingdischarge cells responsible for priming discharge between the frontplate and the back plate. The discharge distance of a priming dischargecell is smaller than that of a main discharge cell, allowing the primingdischarge cell to have the priming discharge with reliability prior tomain discharge (i.e., address discharge). As a further advantage,keeping a proper dielectric voltage between the data electrode and thepriming electrode can improve reliable operations of a PDP.

1. A plasma display panel comprising: a first electrode and a secondelectrode disposed on a first substrate so as to be parallel with eachother; a third electrode disposed on a second substrate confronting thefirst substrate via a discharge space so as to be orthogonal to thefirst electrode and the second electrode; a fourth electrode disposed onthe second substrate so as to be parallel with the first electrode andthe second electrode and to be positioned closer to the first electrodeand the second electrode than the third electrode; and a barrier ribdisposed on the second substrate to separate a plurality of maindischarge cells, which are formed of the first electrode, the secondelectrode, and the third electrode, from a plurality of primingdischarge cells, which are formed of the first electrode and the fourthelectrode or formed of the second electrode and the fourth electrode,wherein, at least the third electrode is covered with a first dielectriclayer and the fourth electrode is disposed on the first dielectriclayer, and the fourth electrode is made of material having a softeningtemperature lower than that of material forming the first dielectriclayer.
 2. The plasma display panel of claim 1, wherein the fourthelectrode is covered with a second dielectric layer, and materialforming the second dielectric layer has a softening temperature notgreater than that of material forming the fourth electrode.
 3. Theplasma display panel of claim 1, wherein material forming the firstdielectric layer has a softening temperature not greater than that ofmaterial forming the third electrode.
 4. The plasma display panel ofclaim 2, wherein the barrier rib is disposed on the second dielectriclayer, and material forming the barrier rib has a softening temperaturenot greater than that of material forming the second dielectric layer.5. A method of manufacturing a plasma display panel comprising: forminga first electrode and a second electrode on a first substrate so as tobe parallel with each other; forming a third electrode on a secondsubstrate confronting the first substrate via a discharge space so as tobe orthogonal to the first electrode and the second electrode; forming afirst dielectric layer to cover the third electrode; forming a fourthelectrode on the first dielectric layer so as to be parallel with thefirst electrode and the second electrode and to be positioned closer tothe first electrode and the second electrode than the third electrode;forming a second dielectric layer to cover the fourth electrode; andforming a barrier rib on the second substrate to separate a plurality ofmain discharge cells, which are formed of the first electrode, thesecond electrode, and the third electrode, from a plurality of primingdischarge cells, which are formed of the first electrode and the fourthelectrode or formed of the second electrode and the fourth electrode,wherein, at least each of the forming of the first dielectric layer, theforming of the fourth electrode, and the forming of the seconddielectric layer includes baking respective paste material for setting,a baking temperature of the baking the fourth electrode is determined tobe lower than a softening temperature of material forming the firstdielectric layer and to be higher than a softening temperature ofmaterial forming the fourth electrode, and a baking temperature of thebaking of the second dielectric layer is determined to be lower than thesoftening temperature of material forming the fourth electrode and to behigher than a softening temperature of material forming the seconddielectric layer.
 6. The method of manufacturing a plasma display panelof claim 5 further includes pattern-forming the barrier rib on thesecond dielectric layer and baking the barrier rib for setting, and abaking temperature of the baking of the barrier rib is not greater thanthe softening temperature of material forming the second dielectriclayer.
 7. A method of manufacturing a plasma display panel comprising:forming a first electrode and a second electrode on a first substrate soas to be parallel with each other; forming a third electrode on a secondsubstrate confronting the first substrate via a discharge space so as tobe orthogonal to the first electrode and the second electrode; forming afirst dielectric layer to cover the third electrode; forming a fourthelectrode on the first dielectric layer so as to be parallel with thefirst electrode and the second electrode and to be positioned closer tothe first electrode and the second electrode than the third electrode;forming a second dielectric layer to cover the fourth electrode; andforming a barrier rib on the second substrate to separate a plurality ofmain discharge cells, which are formed of the first electrode, thesecond electrode, and the third electrode, from a plurality of primingdischarge cells, which are formed of the first electrode and the fourthelectrode or formed of the second electrode and the fourth electrode,wherein, at least each of the forming of the third electrode, theforming of the first dielectric layer, the forming of the fourthelectrode, the forming of the second dielectric layer, and the formingof the barrier rib includes baking respective paste material forsetting; after the baking of the third electrode and the baking of thefirst dielectric layer are simultaneously performed, the baking of thefourth electrode follows, and then the baking of the second dielectriclayer and the baking of the barrier rib are simultaneously performed; abaking temperature of the baking of the fourth electrode is lower thanthe materials forming the third electrode and the first dielectriclayer, and is not less than a softening temperature of material formingthe fourth electrode; and a baking temperature of the baking of thesecond dielectric layer and the barrier rib is lower than the softeningtemperature of material forming the fourth electrode, and is not lessthan a softening temperature of a material having the highest softeningtemperature of materials forming the second dielectric layer and thebarrier rib.
 8. A method of manufacturing a plasma display panelcomprising: forming a first electrode and a second electrode on a firstsubstrate so as to be parallel with each other; forming a thirdelectrode on a second substrate confronting the first substrate via adischarge space so as to be orthogonal to the first electrode and thesecond electrode; forming a first dielectric layer to cover the thirdelectrode; forming a fourth electrode on the first dielectric layer soas to be parallel with the first electrode and the second electrode andto be positioned closer to the first electrode and the second electrodethan the third electrode; forming a second dielectric layer to cover thefourth electrode; and forming a barrier rib on the second substrate toseparate a plurality of main discharge cells, which are formed of thefirst electrode, the second electrode, and the third electrode, from aplurality of priming discharge cells, which are formed of the firstelectrode and the fourth electrode or formed of the second electrode andthe fourth electrode, wherein, at least each of the forming of the thirdelectrode, the forming of the first dielectric layer, the forming of thefourth electrode, the forming of the second dielectric layer, and theforming of the barrier rib includes baking respective paste material forsetting; after the baking of the third electrode and the baking of thefirst dielectric layer are simultaneously performed, the baking of thefourth electrode, the baking of the second dielectric layer, and thebaking of the barrier rib are simultaneously performed; a bakingtemperature of the baking of the fourth electrode, the second dielectriclayer, and the barrier rib is lower than materials forming the thirdelectrode and the first dielectric layer, and is not less than asoftening temperature of a material having the highest softeningtemperature of materials forming the fourth electrode, the seconddielectric layer, and the barrier rib.